1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method. The present invention relates, in particular, to a Wafer Level Chip Size Package (W-CSP) and to a manufacturing method thereof.
2. Description of the Related Art
Recently, in, for example, mobile devices, such as mobile phones and personal digital assistants, extremely high demands are being made for reductions in size, reductions in thickness and reductions in weight in order to give higher performance. Reductions in size, reductions in thickness and reductions in weight are therefore also necessary in individual semiconductor devices (semiconductor packages) on a board of a module mounted in such devices. W-CSP technology is a strong candidate for realizing the above.
W-CSP technology is a technology that, after forming connection terminals directly onto semiconductor elements on a wafer when in the wafer state, uses dicing to divide into individual chip for packaging, without the use of metal lines (wire bonding) in order to lead electrical signals out from a semiconductor device. The semiconductor elements are formed on a silicon wafer or on a compound semiconductor wafer, and have various functions such as, for example, diodes, transistors, and the like. The connection terminals are for electrically connecting to a board of a module. By employing such W-CSP technology, it is possible to reduce mounting surface area and weight to 1/10th or less, that of a package employing conventional die bonding/wire bonding. In this manner, W-CSP technology directly forms connection terminals to the board of the module, directly above a functional region formed with semiconductor elements, such as diodes, transistors or the like. Accordingly, the inherently wasted region is small with W-CSP technology. Further, productively is extremely good with W-CSP technology due processes up to forming the terminals being performed in the wafer state.
FIG. 11 is a schematic configuration diagram for explaining a method of forming a conventional W-CSP. An interlayer insulation film 30 is formed on a single crystal silicon substrate 10, that has been formed with semiconductor elements of various functions, such as, for example, diodes, transistors or the like. Next, metal pads 36 are formed thereon, connected to the semiconductor elements through via holes (not shown) provided in the interlayer insulation film 30. A passivation film 38 is further formed thereon. Next, via holes (not shown) are formed in the passivation film 38 to expose the metal pads 36. Processes up to this stage are referred to as “front-end processes”.
Afterwards, an insulation film 40 is formed of, such as for example, a polyimide, or the like, and via holes (not shown) are formed in the insulation film 40 to expose the metal pads 36. Then metal redistribution lines 44 are formed on the insulation film 40. The metal redistribution lines 44 are connected to the metal pads 36 through the via holes (not shown) formed in the insulation film 40, and the via holes (not shown in) formed in the passivation film 38. Then the metal posts 46 are formed on the metal redistribution lines 44. The sealing resin 50 is then formed. Then the solder terminals 48 are formed on the metal posts 46. Then dicing of the sealing resin 50 and the single crystal silicon substrate 10 is performed with a dicing blade 90.
However, as shown in FIG. 12, in this W-CSP, the side face that has been diced after forming the sealing resin 50 becomes the final side face of the package. Therefore, this W-CSP has a number of weaknesses. One of these is the weakness of moisture absorption in from the package side face. As shown in FIG. 12, the interlayer insulation film 30 is exposed at the package side face after dicing. The interlayer insulation film 30 is an oxidized silicon film formed either by a plasma CVD method, or by a normal pressure CVD method, and the moisture resistance thereof is greatly inferior, in comparison to that of the silicon nitride film employed as the passivation film, the molded resin employed for sealing, or the like.
Structures and manufacturing methods of a semiconductor devices designed to prevent moisture absorption through the interlayer insulation film 30 at the package side wall, are proposed in Japanese Patent Application Laid-Open (JP-A) No. 10-79362, JP-A No. 2000-260910, and JP-A No. 2006-100535. In these structures and manufacturing methods, at a region for exposing the interlayer insulation film 30 in advance prior to mold resin sealing, a dicing cut is inserted partially into the single crystal silicon substrate 10 (half-cut), and the interlayer insulation film 30 is then prevented from being exposed by the subsequent resin sealing.
In such technologies, adhesiveness may deteriorate due to the interlayer insulation film 30 exposed at the package side wall being covered by mold resin. Consequently, adopting different resins for the mold resin and the resin covering the interlayer insulation film 30 exposed at the package side wall could be considered.
In this method, as shown in FIG. 14, the sealing resin 50 is formed in advance, then a half-cut groove 70 is formed partway through the single crystal silicon substrate 10 from the sealing resin 50 side using a dicing blade. Subsequently, as shown in FIG. 13, the half-cut groove 70 is filled with a sealing resin 60 different from the sealing resin 50. Full-cutting into individual chips is performed with a finer dicing blade than that employed when the half-cut groove 70 was formed. By so doing, the interlayer insulation film 30 exposed at the half-cut edge 76 of the dicing in the half-cut groove 70 can be covered by the sealing resin 60 different from the sealing resin 50 used for molding. Consequently, the adhesiveness and the moisture resistance can be raised by this method.
However, in such structures, there is an issue of cracks due to thermal cycling. FIG. 13 shows a crack during thermal cycle testing. Due to full-cutting being performed using a finer dicing blade than that employed when forming the half-cut groove 70, the bottom of the half-cut groove 70 is cut, and large cracks 66 occur in the silicon substrate 10 in the dicing full-cut edge 74, originating from the bottom edge 64 of the half-cut groove 70. These cracks 66 occur due the silicon substrate 10 being unable to forcibly resist resulting thermal stress concentrated at the bottom edge 64 caused by the difference between the coefficients of linear thermal expansion occurring in the differing materials (the sealing resin 60 and the silicon substrate 10) during thermal cycling.
FIG. 14 and FIG. 15, which is an enlarged cross-section of portion B of FIG. 14, show schematically the profile of the half-cut groove 70 of a conventional proposal. The actual half-cut groove 70 is, as schematically shown as a cross-section in FIG. 16, and as shown in the SEM section image of FIG. 17, not completely rectangular, and is of a profile having a rounded portion 62, rounded due to abrasion of the blade tip of the dicing blade. In such cases, the point of stress concentration is, as shown in FIG. 16, the bottom edge 64 of the half-cut groove 70, and stress is concentrated at a single point (in reality a line orthogonal to the plane of the paper). Consequently, the maximum stress becomes is times that of the ideal profile shown in FIG. 15. If the half-cut groove 70 is configured with a vertical side wall 86 and a horizontal bottom 88, then the stress concentration point is the intersection line 84 between the side wall 86 and the bottom 88, and concentration of stress is dissipated by the horizontal bottom portion 88. Accordingly, the maximum stress is smaller when profiled as in FIG. 15 than when the rounded portion 62 of FIG. 16 is formed.
A broad width dicing blade can be employed when the width of the scribe line is wide. Consequently, the profile of the half-cut groove 70 can be made close to that of FIG. 14 and FIG. 15, and the maximum stress can also be held to a small amount. However, when, in order to increase the number of chips obtained, the scribe line width is reduced, a thinner dicing blade must be employed. In such cases, the profile of the bottom of the half-cut groove 70 is not horizontal, and rises more acutely. As a result thereof, profiles like those of FIG. 16 and FIG. 17 arise, stress is concentrated at the bottom edge 64 of the half-cut groove 70, and cracks readily occur due to the large stresses imparted during thermal cycling.